Transforming Vhdl To Timed Automata

Ayav, Tolga; Tuğlular, Tuğkan; Belli, Fevzi

Transforming Vhdl To Timed Automata

Files

25711.pdf (466.54 KB)

Date

2016-12-02

Authors

Ayav, Tolga

Tuğlular, Tuğkan

Belli, Fevzi

Publisher

Izmir Institute of Technology

Organizational Units

Department

03.04. Department of Computer Engineering

Faculty

03. Faculty of Engineering

Institution

01. Izmir Institute of Technology

Abstract

This report presents the transformation of behavioral VHDL programs to Timed Automata.

Description

Technical Report No: IYTE-COMPENG-2015-001

ORCID

Keywords

VHDL, Timed automata

WoS Q

N/A

Scopus Q

N/A

URI

https://hdl.handle.net/11147/2571

Collections

Computer Engineering / Bilgisayar Mühendisliği

Full item page

Page Views

981

checked on Nov 03, 2025

Downloads

376

checked on Nov 03, 2025

Google Scholar™

Check

Transforming Vhdl To Timed Automata

Files

Date

Authors

Journal Title

Journal ISSN

Volume Title

Publisher

Open Access Color

OpenAIRE Downloads

OpenAIRE Views

Research Projects

Organizational Units

Journal Issue

Abstract

Description

ORCID

Keywords

Turkish CoHE Thesis Center URL

Fields of Science

Citation

WoS Q

Scopus Q

Source

Volume

Issue

Start Page

End Page

URI

Collections

Page Views

981

Downloads

376

Google Scholar™

Sustainable Development Goals

SDG data is not available