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https://hdl.handle.net/11147/2553
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DC Field | Value | Language |
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dc.contributor.author | Ayav, Tolga | - |
dc.contributor.author | Tuğlular, Tuğkan | - |
dc.contributor.author | Belli, Fevzi | - |
dc.date.accessioned | 2016-11-30T13:10:53Z | - |
dc.date.available | 2016-11-30T13:10:53Z | - |
dc.date.issued | 2010-07 | - |
dc.identifier.citation | Ayav, T., Tuğlular, T., and Belli, F. (2010, June 9-11). Towards test case generation for synthesizable VHDL programs using model checker. Paper presneted at the 4th IEEE International Conference on Secure Software Integration and Reliability Improvement Companion. doi:10.1109/SSIRI-C.2010.22 | en_US |
dc.identifier.isbn | 9780769540870 | - |
dc.identifier.uri | http://doi.org/10.1109/SSIRI-C.2010.22 | - |
dc.identifier.uri | http://hdl.handle.net/11147/2553 | - |
dc.description | 4th IEEE International Conference on Secure Software Integration and Reliability Improvement Companion, SSIRI-C 2010; Singapore; Singapore; 9 June 2010 through 11 June 2010 | en_US |
dc.description.abstract | VHDL programs are often tested by means of simulations, relying on test benches written intuitively. In this paper, we propose a formal approach to construct test benches from system specification. To consider the real-time properties of VHDL programs, we first transform them to timed automata and then perform model checking against the properties designated from the specification. Counterexamples returned from the model checker serve as a basis of test cases, i.e. they are used to form a test bench. The approach is demonstrated and complemented by a simple case study. | en_US |
dc.language.iso | en | en_US |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | en_US |
dc.relation.ispartof | 4th IEEE International Conference on Secure Software Integration and Reliability Improvement Companion, SSIRI-C 2010 | en_US |
dc.rights | info:eu-repo/semantics/openAccess | en_US |
dc.subject | Test case generation | en_US |
dc.subject | Model checking | en_US |
dc.subject | VHDL | en_US |
dc.subject | Program transformation | en_US |
dc.subject | Timed automata | en_US |
dc.title | Towards test case generation for synthesizable VHDL programs using model checker | en_US |
dc.type | Conference Object | en_US |
dc.authorid | TR114453 | en_US |
dc.authorid | TR114656 | en_US |
dc.institutionauthor | Ayav, Tolga | - |
dc.institutionauthor | Tuğlular, Tuğkan | - |
dc.department | İzmir Institute of Technology. Computer Engineering | en_US |
dc.identifier.startpage | 46 | en_US |
dc.identifier.endpage | 53 | en_US |
dc.identifier.scopus | 2-s2.0-77956097952 | en_US |
dc.relation.publicationcategory | Konferans Öğesi - Uluslararası - Kurum Öğretim Elemanı | en_US |
dc.identifier.doi | 10.1109/SSIRI-C.2010.22 | - |
dc.relation.doi | 10.1109/SSIRI-C.2010.22 | en_US |
dc.coverage.doi | 10.1109/SSIRI-C.2010.22 | en_US |
local.message.claim | 2022-06-03T14:19:15.136+0300|||rp00375|||submit_approve|||dc_contributor_author|||None | * |
item.grantfulltext | open | - |
item.openairecristype | http://purl.org/coar/resource_type/c_18cf | - |
item.cerifentitytype | Publications | - |
item.openairetype | Conference Object | - |
item.languageiso639-1 | en | - |
item.fulltext | With Fulltext | - |
crisitem.author.dept | 03.04. Department of Computer Engineering | - |
crisitem.author.dept | 03.04. Department of Computer Engineering | - |
crisitem.author.dept | 03.04. Department of Computer Engineering | - |
Appears in Collections: | Computer Engineering / Bilgisayar Mühendisliği Scopus İndeksli Yayınlar Koleksiyonu / Scopus Indexed Publications Collection |
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