Kılınççeker, OnurBelli, FevziTürk, ErcümentChallenger, MoharramBelli, Fevzi03.04. Department of Computer Engineering03. Faculty of Engineering01. Izmir Institute of Technology2019-02-202019-02-202018Kılınççeker, O., Türk, E., Challenger, M. and Belli, F. (2018 July 16-20). Regular expression based test sequence generation for HDL program validation. Paper presented at the 18th IEEE International Conference on Software Quality, Reliability, and Security Companion, QRS-C 2018. doi:9781538678398http://doi.org/10.1109/QRS-C.2018.00103http://hdl.handle.net/11147/711918th IEEE International Conference on Software Quality, Reliability, and Security Companion, QRS-C 2018; Lisbon; Portugal; 16 July 2018 through 20 July 2018This paper proposes a test sequence generation approach for behavioral model validation of sequential circuits implemented in Hardware Description Language (HDL). In the procedure of test sequence generation proposed in this study, Regular Expressions (REs) are utilized to model the behavior of the System Under Test (SUT). First, the HDL program is converted to a Finite State Machine (FSM). Then, the obtained FSM is transformed to RE which is represented by a Syntax Tree (ST). In this way, the test sequence generation problem is simplified to the tree traversal algorithm in which symbol and operator coverage criteria are satisfied. The required tools for test sequence generation are provided to automatize the whole procedure of the proposed approach. Also, a running example, based on a real-life-like Traffic Light Controller (TLC), validates the proposed approach and analyzes its characteristic features.eninfo:eu-repo/semantics/openAccessBehavioral modelHardware description languageHardware design validationRegular expressionTest sequence generationConference Object2-s2.0-8505249024710.1109/QRS-C.2018.00103